Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device composed of aplurality of stacked semiconductor chips and to a method for fabricatingthe same.

As an example of the semiconductor device composed of a plurality ofstacked semiconductor chips, a structure has been known in which aplurality of semiconductor chips are mounted in stacked relation on aboard termed an interposer or a substrate, which are sealed with a moldresin (see, e.g., page 7 and FIG. 3 of Japanese Laid-Open PatentPublication No. HEI 11-204720). This type of semiconductor device isalso referred to as a stacked package. An object of forming thesemiconductor device in such a multilayer-chip-type structure is toincrease the mounting density of the semiconductor chips.

FIGS. 5A and 5B show a conventional multilayer-chip-type semiconductordevice, of which FIG. 5A is a cross-sectional view and FIG. 5B is a planview.

In FIGS. 5A and 5B, a first semiconductor chip 103 having bumps 103 aare mounted with the bumps 103 a facing downward on a substrate 101having electrode pads 101 a on the upper surface thereof and lands 101 bon the lower surface thereof with a first adhesion layer 102 interposedtherebetween. A second semiconductor chip 105 having electrodes pads 105a on the upper surface thereof is mounted on the first semiconductorchip 103 with a second adhesion layer 104 interposed therebetween. Theelectrodes pads 105 a of the second semiconductor chip and the electrodepads 101 a of the substrate 101 are electrically bonded to each otherwith wires 107. The first semiconductor chip 103, the secondsemiconductor chip 105, and the wires 107 are sealed with a mold resin108, whereby the semiconductor device is formed.

The first adhesion layer 102 is composed of a film-like adhesive or aliquid adhesive which is filled in the entire region other than thebumps 103 a between the substrate 101 and the first semiconductor chip103 to firmly fix the first semiconductor chip 103 to the chip mountingregion of the substrate 101. The arrangement disperses a stress over theentire chip mounting region of the substrate 101 and thereby increasesthe reliability of the semiconductor device.

In the conventional multilayer-chip-type semiconductor device, theperipheral edge portion of the first adhesion layer 102 is protrudingoutwardly from the peripheral edge portion of the first semiconductorchip 103, as shown in FIGS. 5A and 5B. This causes a first problem that,due to the protrusion (fillet) 102 a, the size reduction of thesemiconductor device is difficult. Since the wires 107 providing bondingbetween the electrode pads 105 a of the second semiconductor chip 105and the first electrode pads 101 a of the substrate 101 should bedisposed externally of the protrusion 102 a of the first adhesion layer102, i.e., since the electrode pads 101 a of the substrate 101 should bedisposed externally of the protrusion 102 a of the first adhesion layer102, the area of the substrate 101 is inevitably increased so that thesize reduction of the semiconductor device is difficult.

The conventional multilayer-chip-type semiconductor device also has asecond problem that the reliability thereof lowers due to the protrusion102 a of the first adhesion layer 102. Since the wires 107 should bedisposed externally of the protrusion 102 a of the first adhesion layer102, as described above, the lengths of the wires 107 are increaseddisadvantageously. This causes a phenomenon in which the wires 107 aredeformed by the mold resin 108 in sweeping motion in the step ofinjecting the mold resin 108 in a mold (the phenomenon is termed wiresweep or wire flow) so that such a defect as the breakage of the wire107 or a short circuit between the adjacent wires 107 is more likely tooccur. As the lengths of the wires 107 increase, the fluidity of themold resin 108 is reduced so that, in some cases, an unfilled portion ora void occurs in the mold resin 108 to reduce the reliability of thesemiconductor device 108. The second problem is conspicuously observedin a semiconductor device having the wires 107 at a high density.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to simultaneouslysolve the first and second problems and thereby provide a smaller-sizemultilayer-chip-type semiconductor device with higher reliability.

To attain the object, a semiconductor device according to the presentinvention comprises: a substrate having an electrode pad; a firstsemiconductor chip mounted on the substrate with a first adhesion layerinterposed therebetween; a second semiconductor chip mounted on thefirst semiconductor chip with a second adhesion layer interposedtherebetween and having an electrode pad on an upper surface thereof; awire for bonding the electrode pad of the substrate and the electrodepad of the second semiconductor chip to each other; and a mold resinsealing therein the first and second semiconductor chips and the wire,the first adhesion layer having a peripheral edge portion protrudingoutwardly from the first semiconductor chip, the second semiconductorchip having a peripheral edge portion protruding outwardly beyond aperipheral edge portion of the first semiconductor chip.

In the semiconductor device according to the present invention, theperipheral edge portion of the second semiconductor chip is protrudingoutwardly beyond the peripheral edge portion of the first semiconductorchip. The arrangement prevents the situation in which the area of thesubstrate should be increased by the magnitude of the area occupied bythe portion of the first adhesion layer protruding outwardly from thefirst semiconductor chip, which is observed in the conventionalembodiments, so that a smaller-size multilayer-chip-type semiconductordevice is implemented. The arrangement also prevents the situation inwhich the length of the wire should be increased by the length of theportion thereof located outside the protrusion of the first adhesionlayer, which is also observed in the conventional embodiment. As aresult, the influence of wire sweep occurring in the step of injecting amold resin in a mold can be suppressed and a short circuit between wirescan be prevented so that a semiconductor device with higher reliabilityis implemented.

In the semiconductor device according to the present invention, theperipheral edge portion of the second semiconductor chip is preferablyprotruding outwardly beyond the peripheral edge portion of the firstadhesion layer.

In the arrangement, the peripheral edge portion of the first adhesionlayer does not protrude outwardly beyond the peripheral edge portion ofthe second semiconductor chip so that a further-smaller-sizesemiconductor device with further higher reliability is implemented.

In the semiconductor device according to the present invention, a centerof the second semiconductor chip is preferably offset from a center ofthe first semiconductor chip.

The arrangement allows proper adjustment the amount of outwardprotrusion of the peripheral edge portion of the second semiconductorchip from the peripheral edge portion of the first semiconductor chip inaccordance with the amount of outward protrusion of the peripheral edgeportion of the first adhesion layer from the first semiconductor chip.

In the semiconductor device according to the present invention, thecenter of the second semiconductor chip is preferably offset from thecenter of the first semiconductor chip in a direction of an edge of theperipheral edge portion of the first adhesion layer which is protrudingmost outwardly from the first semiconductor chip.

In the arrangement, the center of the second semiconductor chip isoffset from the center of the first semiconductor chip in a direction ofthe edge of the peripheral edge portion of the first adhesion layerwhich is protruding most outwardly from the first semiconductor chip sothat the portion of the first adhesion layer which is protruding mostoutwardly is located under the second semiconductor chip. Thisimplements a smaller-size semiconductor device with higher reliability.

In the semiconductor device according to the present invention, thecenter of the second semiconductor chip is preferably offset from thecenter of the first semiconductor chip in a direction of an edge of theperipheral edge portion of the first adhesion layer which has a largestsurface height from the substrate.

In the arrangement, the portion of the first adhesion layer which isprotruding most outwardly is located under the second semiconductor chipso that a smaller-size semiconductor device with higher reliability isimplemented.

In the semiconductor device according to the present invention, thecenter of the second semiconductor chip substantially preferablycoincides with a center of the substrate.

The arrangement allows a stress balance in the semiconductor device tobe closer to symmetry relative to the center of the substrate and alsoallows the lengths of the wires and the loop configurations thereof tobe closer to uniformity at the four edge sides of the secondsemiconductor chip. As a result, operation stability in wire bonding isincreased and a production yield is increased, while the time requiredfor the operation is reduced.

A method for fabricating a semiconductor device according to the presentinvention comprises: a first step of disposing a first semiconductorchip on a substrate having an electrode pad; a second step of injectingan adhesive in a space between the substrate and the first semiconductorchip to form a first adhesion layer composed of the adhesive and havinga peripheral edge portion protruding outwardly from the firstsemiconductor chip; a third step of mounting, on the first semiconductorchip, a second semiconductor chip having an electrode pad on aperipheral edge portion of an upper surface thereof with a secondadhesion layer interposed therebetween; a fourth step of bonding theelectrode pad of the substrate and the electrode pad of the secondsemiconductor chip to each other with a wire; and a fifth step ofsealing the first and second semiconductor chips and the wire with amold resin, the third step including the step of protruding a peripheraledge portion of the second semiconductor chip outwardly beyond aperipheral edge portion of the first semiconductor chip.

In the method for fabricating a semiconductor device according to thepresent invention, the peripheral edge portion of the secondsemiconductor chip is protruded outwardly beyond the peripheral edgeportion of the first semiconductor chip. The arrangement prevents thesituation in which the area of the substrate should be increased by thearea occupied by the portion of the first adhesion layer which isprotruding outwardly from the first semiconductor chip, which isobserved in the conventional embodiments, so that a smaller-sizemultilayer-chip-type semiconductor device is implemented. Thearrangement also prevents the situation in which the length of the wireshould be increased by the length of the portion thereof located outsidethe protrusion of the first adhesion layer, which is also observed inthe conventional embodiment. As a result, the influence of wire sweepoccurring in the step of injecting a mold resin in a mold can besuppressed and a short circuit between wires can be prevented so that asemiconductor device with higher reliability is implemented.

In the method for fabricating a semiconductor device according to thepresent invention, the third step preferably includes the step ofprotruding the peripheral edge portion of the second semiconductor chipoutwardly beyond the peripheral edge portion of the first adhesionlayer.

In the arrangement, the peripheral edge portion of the first adhesionlayer does not protrude outwardly beyond the peripheral edge portion ofthe second semiconductor chip so that a further-smaller-sizesemiconductor device with further higher reliability is implemented.

In the method for fabricating a semiconductor device according to thepresent invention, the first step preferably includes the step ofdisposing the first semiconductor chip such that a center of the firstsemiconductor chip is offset from a center of the substrate in adirection of an edge of the first semiconductor chip opposite to adirection of an edge thereof from which the adhesive is injected in thesecond step.

In the arrangement, the adhesive protrudes most outwardly from the firstsemiconductor chip along the edge from which the adhesive is injected sothat the portion of the adhesive which is protruding most outwardly fromthe first semiconductor chip is located under the second semiconductorchip. This implements a smaller-size semiconductor device with higherreliability.

In the method for fabricating a semiconductor device according to thepresent invention, the third step preferably includes the step ofmounting the second semiconductor chip such that a center of the secondsemiconductor chip is offset from a center of the first semiconductorchip.

The arrangement allows proper adjustment the amount of outwardprotrusion of the peripheral edge portion of the second semiconductorchip from the peripheral edge portion of the first semiconductor chip inaccordance with the amount of outward protrusion of the peripheral edgeportion of the first adhesion layer from the first semiconductor chip.

In the method for fabricating a semiconductor device according to thepresent invention, the third step preferably includes the step ofmounting the second semiconductor chip such that the center of thesecond semiconductor chip is offset from the center of the firstsemiconductor chip in a direction of an edge of the first semiconductorchip from which the adhesive is injected in the second step.

In the arrangement, the adhesive protrudes most outwardly from the firstsemiconductor chip along the edge from which the adhesive is injected sothat the portion of the adhesive which is protruding most outwardly fromthe first semiconductor chip is located under the second semiconductorchip. This implements a smaller-size semiconductor device with higherreliability.

In the method for fabricating a semiconductor device according to thepresent invention, the third step preferably includes the step ofmounting the second semiconductor chip such that a center of the secondsemiconductor chip substantially coincides with a center of thesubstrate.

The arrangement allows a stress balance in the semiconductor device tobe closer to symmetry relative to the center of the substrate and alsoallows the lengths of the wires and the loop configurations thereof tobe closer to uniformity at the four edge sides of the secondsemiconductor chip. As a result, the stability of a wire bondingoperation is increased and a production yield is increased, while thetime required for the operation is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional view of a multilayer-chip-typesemiconductor device according to a first embodiment of the presentinvention and FIG. 1B is a plan view of the multilayer-chip-typesemiconductor device according to the first embodiment;

FIG. 2A is a cross-sectional view of a multilayer-chip-typesemiconductor device according to a second embodiment of the presentinvention and FIG. 2B is a plan view of the multilayer-chip-typesemiconductor device according to the second embodiment;

FIGS. 3A to 3E are cross-sectional views illustrating, in the order ofprogression, the individual process steps of a method for fabricating amultilayer-chip-type semiconductor device according to a thirdembodiment of the present invention;

FIG. 4 is a cross-sectional view of the multilayer-chip-typesemiconductor device according to the fourth embodiment; and

FIG. 5A is a cross-sectional view of a conventional multilayer-chip-typesemiconductor device and FIG. 5B is a plan view of the conventionalmultilayer-chip-type semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION EMBODIMENT 1

A semiconductor device according to first embodiment of the presentinvention will be described herein below with reference to FIGS. 1A and1B.

FIGS. 1A and 1B show a multilayer-chip-type semiconductor deviceaccording to the first embodiment, of which FIG. 1A is a cross-sectionalview and FIG. 1B is a plan view.

In the present semiconductor device, as shown in FIGS. 1A and 1B, asquare first semiconductor chip 12 having bumps 12 a is mounted with thebumps 12 a facing downward on a square substrate 10 having electrodepads 1 a on the region of the upper surface thereof located outside achip mounting region and lands 10 b on the lower surface thereof with afirst adhesion layer 11 interposed therebetween. A square secondsemiconductor chip 14 having electrode pads 14 a along the peripheraledge portion of the upper surface thereof is mounted on the firstsemiconductor chip 12 with a second adhesion layer 13 interposedtherebetween. The electrode pads 14 a of the second semiconductor chip14 and the electrode pads 10 a of the substrate 10 are electricallybonded to each other with wires 15. The first semiconductor chip 12, thesecond semiconductor chip 14, and the wires 15 are sealed with a moldresin 16, whereby the semiconductor device is formed.

The substrate 10 is a sheet-like insulator internally provided with aconductor for providing electrical bonding between the electrode pads 10a and the lands 10 b. The substrate 10 has the function of electricallyinterconnecting a mother board (not shown), on which the semiconductordevice according to the first embodiment is mounted, with the firstsemiconductor chip 12 and the second semiconductor chip 14. As theinsulator of the substrate 10, ceramic such as alumina, epoxy, BT resin,polyimide, or the like is used. As the internal conductor, copper,tungsten, or the like is used. The lands 10 b are typically arranged ina grid-like configuration and used for the mounting of the semiconductordevice to the mother board. Although FIG. 1A shows the semiconductordevice of LGA (Land Grid Array) type using the lands 10 b, asemiconductor device of BGA (Ball Grid Array) type using metal ballsinstead of the lands 10 b may also be used instead.

The first adhesion layer 11 has the functions of firmly fixing thesubstrate 10 and the first semiconductor chip 12 to each other andmaintaining the reliability of flip-chip bonding between the substrate10 and the bumps 12 a. As an adhesion composing the first adhesion layer11, a thermosetting resin containing an epoxy resin or the like as amain component can be used primarily. It is possible to use an adhesivewhich is in a liquid state or in a film-like configuration before it isthermoset. Selection can be made depending on required characteristicsor a formation method. As an example of the formation method using aliquid adhesive, there can be listed a method in which a liquid adhesiveis supplied dropwise to the outside of the first semiconductor chip 12mounted on the substrate 10. In accordance with the method, the liquidadhesive is filled by capillarity into the space between the substrate10 and the first semiconductor chip 12 so that, if it is set in asetting furnace thereafter, the first adhesion layer 11 is formed. As anexample of the formation method using a film-like adhesive, on the otherhand, there can be listed a method in which a film-like adhesive isapplied temporarily to the substrate 10 and then the first semiconductorchip 12 is thermally compression bonded onto the adhesive. Electricalbonding may also be provided between the substrate 10 and the bumps 12 aby using an anisotropic conductive film, as the first adhesion layer 11,in which a conductive filler is dispersed and a plated bump as the bump12 a. Further, in the case where the first adhesive layer 11 is made ofan insulating film, electrical bonding may be provided between thesubstrate 10 and the bumps 12 a by piercing the film layer with the useof a stud bump or a printed bump as the bump 12 a. In this case, thesame formation method as described above is used in the case of using afilm-like adhesive. In the case of using a liquid adhesive, however, aformation method different from the one described above is used, whichcoats a liquid adhesive onto the substrate 10, mounts the firstsemiconductor chip 12 on the adhesive, and then thermosetting the liquidadhesive. In some cases, a liquid adhesion may also be termed anunderfill irrespective of the presence or absence of a conductivefiller.

The second adhesion layer 13 has the function of fixing the first andsecond semiconductor chips 12 and 14 to each other. As an adhesivecomposing the second adhesion layer 13, a thermosetting resin containingan epoxy resin or the like as a main component may be used primarily inthe same manner as in the first adhesion layer 11. It is also possibleto use an adhesive which is in a liquid state or in a film-likeconfiguration before it is thermoset. Selection can be made depending onrequired characteristics or a formation method. The second adhesionlayer 13 shown in FIG. 1A shows the case where a filter-like adhesive isused. In a typical formation method using a film-like adhesive, theadhesive is applied to the back surfaces of the second semiconductorchips 14 in the form of a wafer. The film-like adhesive is cut intopieces of the same size as the individual second semiconductor chips 14when they are separated from each other and each of the adhesive piecesis thermally compression bonded to the first semiconductor chip 12. Inanother formation method using a film-like adhesive, the film-likeadhesive is wound into a roll and a portion thereof having a proper areais cut out of the roll by using a cutter, which is thermally compressionbonded to the first semiconductor chip 12. Thereafter, the secondsemiconductor chip 14 is thermally compression bonded onto the adhesive.As an example of the formation method using a liquid adhesive, there canbe listed a method in which the adhesive 5 is supplied dropwise onto thefirst semiconductor chip 12 at a room temperature. After the secondsemiconductor chip 14 is mounted on the adhesive, the resultingstructure is placed in a setting furnace such that the liquid adhesiveis thermoset.

Although a wafer made of Si is used normally for the first and secondsemiconductor chips 12 and 14, it is also possible to use a wafer madeof a compound semiconductor such as SiGe, GaAs, or GaP instead. Thefirst and second semiconductor chips 12 and 14 may be made of the samematerial or different materials.

The bumps 12 a are made of Ag, Au, Cu, a solder, or the like. As anexample of a method for forming the bumps 12 a, there can be listedprinting, mask vapor deposition, stud bump formation, plating, bumptransfer, or the like. As an example of the method for bonding the bumps12 a to the substrate 10, there can be listed a method which meltssolder bumps for bonding, a method which adds a conductive paste to thebumps 12 a for bonding, a method which compression bonds the bumps 12 athrough the set shrinkage of the first adhesion layer 11, a method whichbonds the bumps 12 a by using an ultrasonic wave. Selection can be madeappropriately depending on the material of the bumps 12 a.

The wires 15 are typically made of Au, Al, or the like and has thefunction of providing electrical bonding between the electrode pads 14 aof the second semiconductor chip 14 and the electrode pads 10 a of thesubstrate 10. As a bonding method using the wires 15, thermosonicbonding is used primarily.

The mold resin 16 is typically composed of an epoxy resin. Depending ona molding method, an epoxy resin which is in a solid or liquid statebefore setting can be used selectively. As a formation method for themold resin 16, a transfer method can be listed in the case of using asolid resin and a potting or printing method can be listed in the caseof using a liquid resin. In the transfer method, a resin formed as atablet is melt in a mold, injected under pressure into an inner space ofthe mold in which objects to be sealed are held, and then set in asetting furnace, so that the mold resin 16 is formed. In the pottingmethod, a resin is coated on objects to be sealed and then set in a setfurnace, so that the mold resin 16 is formed. In the printing method, ascreen mask is brought into close contact with objects to be sealed anda mold resin is transferred into an opening in the screen mask by usinga printing squeezer. After the screen mask is removed, the mold resin isset in a setting furnace, so that the mold resin 16 is formed. It iseffective in preventing voids to perform the process according to theprinting method partly in a vacuum chamber. In the mold resin 16, asilica filler is normally mixed in a proportion of 60 wt % to 80 wt %.

In the multilayer-chip-type semiconductor device according to the firstembodiment, the peripheral edge portion of the first adhesion layer 11is protruding outwardly beyond the peripheral edge portion of the firstsemiconductor chip 12, while the peripheral edge portion of the secondsemiconductor chip 14 is protruding more outwardly than the protrusion11 a, as shown in FIG. 1A. Briefly, the peripheral edge portion of thefirst adhesion layer 11 is not protruding outwardly beyond theperipheral edge portion of the second semiconductor chip 14. Thisprevents the situation in which the area of the substrate 10 should beincreased by the magnitude of the area occupied by the protrusion 11 aof the first adhesion layer 11, which is observed in the conventionalembodiments, so that a smaller-size multilayer-chip-type semiconductordevice is implemented.

In addition, the peripheral edge portion of the first adhesion layer 11is not protruding outwardly beyond the peripheral edge portion of thesecond semiconductor chip 14. This prevents the situation in which thelengths of the wires 15 should be increased by the lengths of theportions thereof located outside the protrusion 11 a of the firstadhesion layer 11, which is also observed in the conventionalembodiments. As a result, the influence of wire sweep occurring in thestep of injecting a resin before setting, which will form the mold resin16, can be suppressed and a short circuit between the wires can beprevented so that a semiconductor device with higher reliability isimplemented.

A description will be given next by using a specific example. If thefirst adhesion layer 11 is made of, e.g., an adhesive composed of afilm-like resin, the distance between the peripheral edge portion of thefirst semiconductor chip 11 and the peripheral edge portion of theprotrusion 11 a of the first semiconductor chip 11 as the length of theprotrusion 11 a is about 1 mm at the maximum. If the peripheral edgeportion of the second semiconductor chip 14 is assumed to be protrudingoutwardly beyond the peripheral edge portion of the first semiconductorchip 12 by about 2 mm in each of vertical and horizontal directions, theprotrusion 11 a of the first adhesion layer 11 does not protrude beyondthe peripheral edge portion of the second semiconductor chip 14.

Consideration will be given to the case where the first and secondsemiconductor chips 12 and 14 are mounted by switching the respectivevertical positions thereof shown in FIG. 1A, i.e., to the case (notshown) where the second semiconductor chip 14 is mounted on thesubstrate 10 with the first adhesion layer 11 interposed therebetween,the first semiconductor chip 12 is mounted on the second semiconductorchip 14 with the second adhesion layer 13 interposed therebetween, andthe first semiconductor chip 12 and the substrate 10 are bonded to eachother with the wires 15 via the electrode pads. As described above, itis assumed that the length of the second semiconductor chip 14 is largerby about 2 mm than the length of the first semiconductor chip 12 and thelength of the protrusion 11 a of the first adhesion layer 11 is about 1mm at the maximum. In this case, it is necessary to provide thesubstrate 10 with an extra area corresponding to the maximum length(about 1 mm×2) of the protrusion 11 a. In the semiconductor device shownin FIG. 1A, by contrast, the area of the substrate 10 need not beincreased as stated previously. Compared with the case where the firstand second semiconductor chips 12 and 14 are mounted by switching therespective vertical positions thereof, the size of the substrate 10 neednot be increased any more by about 2 mm in each of vertical andhorizontal directions so that a smaller-size semiconductor device isimplemented. Since each of the wires 15 should be extended from thefirst semiconductor chip 12, which is smaller by 2 mm than the secondsemiconductor chip 14, to a point external of the protrusion 11 a of thefirst adhesion layer 11, it is necessary to elongate the wire by about 2mm compared with the case of the multilayer-chip-type semiconductordevice shown in FIG. 1A. Accordingly, the lengths of the wires 15 can bereduced in the semiconductor device shown in FIG. 1A, compared with thecase where the first and second semiconductor chips 12 and 14 aremounted by switching the respective vertical positions thereof, so thata semiconductor device with higher reliability is implemented.

The foregoing description has been given to the case where theperipheral edge portion of the second semiconductor chip 14 isprotruding outwardly beyond the peripheral edge portion of theprotrusion 11 a of the first adhesion layer 11, as shown in FIG. 1A.This is because the area of the substrate 10 and the lengths of thewires 15 can be minimized in this case and hence it is most preferableas an embodiment. However, the present embodiment is not limitedthereto. For example, a smaller-size multilayer-chip-type semiconductordevice with higher reliability can be implemented provided that theperipheral edge portion of the second semiconductor chip 14 isprotruding even slightly outwardly beyond the peripheral edge portion ofthe first semiconductor chip 12. This is because, so long as theperipheral edge portion of the protrusion 11 a of the first adhesionlayer 11 is protruding outwardly beyond the peripheral edge portion ofthe second semiconductor chip 14 even slightly, the area of thesubstrate 10 can be reduced by the area occupied by the portion of theprotrusion 11 a located under the peripheral edge portion of the secondsemiconductor chip 14 so that a smaller-size multilayer-chip-typesemiconductor device with higher reliability is implemented.

As shown in FIG. 1B, the present embodiment has described the case wherethe plan configuration of each of the first and second semiconductorchips 12 and 14 is a rectangle. Even if the plan configuration of eachof the first and second semiconductor chips 12 and 14 is a rectangle,however, at least a part of the protrusion 11 a of the first adhesionlayer 11 is located under the second semiconductor chip 14 provided thatthe peripheral edge portion of the second semiconductor chip 14 isprotruding outwardly beyond the peripheral edge portion of the firstsemiconductor chip 12. As a result, a smaller-size semiconductor devicewith higher reliability is implemented. It is not necessary for each ofthe four sides on the periphery of the second semiconductor chip 14 toprotrude outwardly from the corresponding one of the four sides on theperiphery of the first semiconductor chip 12. If the secondsemiconductor chip 14 is mounted to have a peripheral edge portionprotruding outwardly beyond the peripheral edge portion of the firstsemiconductor chip 12 such that at least a part of the peripheral edgeportion of the protrusion 11 a of the first adhesion layer 11, which isprotruding most outwardly from the first semiconductor chip 12, islocated under the second semiconductor chip 14, a smaller-sizesemiconductor device with higher reliability can be implemented.

EMBODIMENT 2

A semiconductor device according to a second embodiment of the presentinvention will be described with reference to FIGS. 2A and 2B.

FIGS. 2A and 2B are views for illustrating the semiconductor deviceaccording to the second embodiment, of which FIG. 2A is across-sectional view and FIG. 2B is a plan view.

In FIGS. 2A and 2B, the center axis A of the second semiconductor chip14, the center axis B of the first semiconductor chip 12, and the centeraxis C of the substrate 10 are shown.

In the present semiconductor device, a square first semiconductor chip12 having bumps 12 a is mounted with the bumps 12 a facing downward on asquare substrate 10 having electrode pads 10 a on the upper surfacethereof and having lands 10 b on the lower surface thereof with a firstadhesion layer 11 interposed therebetween, as shown in FIGS. 2A and 2B.A square second semiconductor chip 14 having electrode pads 14 a on theperipheral edge portion of the upper surface thereof is mounted on thefirst semiconductor chip 12 with a second adhesion layer 13 interposedtherebetween. The electrode pads 14 a of the second semiconductor chip14 and the electrode pads 10 a of the substrate 10 are electricallybonded to each other with wires 15. The first and second semiconductorchips 12 and 14 and the wires 15 are sealed with a mold resin 16,whereby the semiconductor device is formed.

As shown in FIGS. 2A and 2B, the present embodiment has mounted thesecond semiconductor chip 14 on the first semiconductor chip 12 with thesecond adhesion layer 13 interposed therebetween such that the centeraxis A of the second semiconductor chip 14 coincides with the centeraxis C of the substrate 10. The present embodiment has also mounted thefirst semiconductor chip 12 on the substrate 10 with the first adhesionlayer 11 interposed therebetween while offsetting the center axis B ofthe first semiconductor chip 12 from the center axis A of the secondsemiconductor chip 14 and from the center axis C of the substrate 10such that the first semiconductor chip 12 is not coaxial with the secondsemiconductor chip 14 and with the substrate 10. The direction in whichthe center axis B of the first semiconductor chip 12 is offset when itis mounted is opposite to the direction of the edge of the protrusion 11a of the first adhesion layer 11 which is protruding most outwardly fromthe first semiconductor chip 12. In other words, the center axis A ofthe second semiconductor chip 14 is offset from the center axis B of thefirst semiconductor chip 12 in the direction of that one of the edges ofthe protrusion 11 a of the first adhesion layer 11 which is protrudingmost outwardly from the first semiconductor chip 12.

Even if the peripheral edge portion of the protrusion 11 a of the firstadhesion layer 11 is protruding outwardly from the first semiconductorchip 12 and an amount of protrusion is non-uniform along the edges ofthe first adhesion layer 11, the second semiconductor chip can have theperipheral edge portion thereof protruding outwardly beyond theperipheral edge portion of the first adhesion layer 11 by mounting thefirst semiconductor chip 12 such that the center axis B thereof isoffset from the center axis A of the second semiconductor chip 14 andfrom the center axis C of the substrate 10. This prevents the situationin which the area of the substrate 10 should be increased by the areaoccupied by the protrusion 11 a of the first adhesion layer 11, whichhas been observed conventionally, so that a smaller-sizemultilayer-chip-type semiconductor device is implemented. This alsoprevents the situation in which the lengths of the wires 15 should beincreased by the lengths of the portions of the wires 15 located outsidethe protrusion 11 a of the first adhesion layer 11. As a result, theinfluence of wire sweep occurring in the step of injecting the moldresin 16 in a mold can be suppressed and a short circuit between thewires can be prevented so that the reliability of the semiconductordevice is increased.

A description will be given next to advantages obtained by coincidingthe center axis A of the second semiconductor chip 14 with the centeraxis C of the substrate 10.

The first advantage is that a stress balance in the semiconductor devicecan be brought closer to symmetry relative to each of the center axes Aand C by coinciding the center axis A of the second semiconductor chip14, which is a largest structure in the mold resin 16, with the centeraxis C of the substrate 10 in the multilayer-chip-type semiconductordevice. This reduces the localization of stresses occurring when thedistribution of stresses in the semiconductor device is uneven during,e.g., reflow mounting and prevents the degradation of the semiconductordevice.

The second advantage is that the lengths of the wires 15 and the loopconfigurations thereof can be brought closer to uniformity along thefour edge sides of the second semiconductor chip 14. This increasesoperation stability in the wire bonding step compared with the casewhere the respective lengths of the wires 15 are not uniform, increasesa yield rate, and reduces the time required for the step. It is alsopossible to achieve the same effect as achieved by the second advantageby designing a wiring pattern for the substrate 10 such that the lengthsof the wires 15 are uniform without coinciding the center axis A withthe center axis C.

Although the description has been given thus far to the case where thecenter axis A is made coincident with the center axis C, it will easilybe appreciated that the same effect is achievable by positioning thecenter axes A and C such that they are nearly coincident.

It is also possible to dispose the first and second semiconductor chips12 and 14 on the substrate 10 such that the center axis B of the firstsemiconductor chip 12 is coincident with the center axis C of thesubstrate 10 and that the center axis A of the second semiconductor chip14 is offset from the center axis B of the first semiconductor chip 12and from the center axis C of the substrate 10 or dispose the first andsecond semiconductor chips 12 and 14 on the substrate 10 such that therespective center axes A, B, and C are offset from each other and arenot coincident. In either of the cases, if the peripheral edge of thesecond semiconductor chip 14 has a portion protruding beyond theperipheral edge portion of the first semiconductor chip 12, thesemiconductor device can be reduced in size by the area of the portionof the protrusion ha of the first adhesion layer 11 located under theprotruding portion. The directions in which the center axes A and B ofthe second and first semiconductor chips 14 and 12 are offset from thecenter axis C of the substrate 10 and the amounts of offsetting in thesecases may be determined appropriately by examining the respectiveconfigurations and areas of the first and second semiconductor chips 12and 14, the substrate 10, and the protrusion 11 a of the first adhesionlayer 11, the lengths of the wires 15, and the like such that optimumdesign which enables maximum miniaturization of the semiconductor deviceis performed.

EMBODIMENT 3

A semiconductor device according to a third embodiment of the presentinvention will be described with reference to FIGS. 3A to 3E.

FIGS. 3A to 3E are cross-sectional views illustrating, in the order ofprogression, the individual steps of a method for fabricating thesemiconductor device according to the third embodiment.

FIG. 3A is a view showing the first step. In the present step termed aflip chip bonding step, a first semiconductor chip 12 is disposed on asubstrate 10 having electrode pads (not shown). In this step,positioning is performed such that bumps 12 a provided on the firstsemiconductor chip 12 are connected to the electrode pads (not shown) ofthe substrate 10 and the first semiconductor chip 12 is mounted suchthat the bumps 12 a face downward. It is also possible to connect thebumps 12 a to the electrode pads of the substrate 10 by adding aconductive paste to the bumps 12 a. If the first semiconductor chip 12is mounted on the substrate 10 such that the center axis B of the firstsemiconductor chip 12 is offset from the center axis C of the substrate10 in a direction of the edge opposite to the edge from which anadhesive is injected, a portion for reserving the adhesive (hereinafterreferred to as a reserving portion) formed in injecting the adhesive canbe formed to occupy a large space.

FIG. 3B is a view showing the second step. In the present step termed anunderfill step, an adhesive is injected into the space between thesubstrate 10 and the first semiconductor chip 12 to form a firstadhesion layer 11 composed of the adhesive and having a peripheral edgeportion protruding outwardly from the first semiconductor chip 12. Inthe case of injecting a liquid adhesive into the space between the firstsemiconductor chip 12 and the substrate 10, a nozzle 17 is positioned onthe outer edge of the first semiconductor chip 12 to eject the adhesive.If necessary, the nozzle 17 is moved reciprocally along the edge sidefrom which the adhesive is injected to eject the adhesive so that theportion for reserving a required amount of the adhesive to be injectedis formed. The adhesive is filled from the reserving portion by thesurface tension of the adhesive into the space between the firstsemiconductor chip 12 and the substrate 10. When the filling of theadhesive is completed, the injected adhesive is set so that the firstadhesion layer 11 is formed.

A specific description will be given to the protrusion 11 a of the firstadhesion layer 11. If consideration is given to the case where, e.g.,the adhesive is injected from one of the edge sides of the firstsemiconductor chip 12, the reserving portion is formed around the oneedge side so that the protruding length and height of the protrusion 11a of the adhesive are larger along the edge side than along the otherthree edge sides. Although fillets are formed naturally along the otherthree edge sides, the protruding lengths and heights thereof are not aslarge as those of the protrusion 11 a from the edge side formed with thereserving portion. Specifically, the protruding length of the protrusion11 a is about 2 mm at the maximum along the edge side formed with thereserving portion, while it is about 0.5 mm along the other three edgesides. Thus, the peripheral edge portion of the protrusion 11 a of theadhesive is larger in protruding length and height along one of the fouredge sides than along the other three edge sides.

The configuration of the protrusion 11 a of the first adhesion layer 11can be controlled by optimizing a condition such as the material of theadhesive to be used, an amount of injection, an injection time, or asetting temperature. In this case, a smaller-size semiconductor devicecan be implemented by controlling the configuration of the protrusion 11a such that the protrusion 11 a does not protrude beyond the peripheraledge portion of the second semiconductor chip 14 to be mounted in a stepwhich will be described later.

FIG. 3C is a view showing the third step. In the present step termed astacked die bonding step, the second semiconductor chip 14 havingelectrode pads along the peripheral edge portion of the upper surfacethereof is mounted on the first semiconductor chip 12 with the secondadhesion layer 13 interposed therebetween. At this time, the secondsemiconductor chip 14 is mounted on the first semiconductor chip 12 withthe second adhesion layer 13 interposed therebetween such that theportion of the peripheral edge of the protrusion 11 a of the adhesivewhich is protruding most outwardly from the first semiconductor chip 12does not protrude beyond the peripheral edge portion of the secondsemiconductor chip 14 so that a smaller-size semiconductor chip isimplemented. If consideration is given to the fact that the protrudinglength from the first semiconductor chip 12 along the edge side formedwith the reserving portion is about 2 mm at the maximum, the position atwhich the second semiconductor chip 14 is mounted when the secondsemiconductor chip 14 is larger by 1 mm than the first semiconductorchip 12 in each of vertical and horizontal directions is shifted by 1 mmfrom the center axis B of the first semiconductor chip 12 in thedirection of the position at which the reserving portion is formed.Consequently, the peripheral edge portion of the second semiconductorchip 14 protrudes by 2 mm from the peripheral edge portion of the firstsemiconductor chip 12 so that the most outwardly extending portion ofthe protrusion 11 a does not protrude beyond the peripheral edge of thesecond semiconductor chip 14.

This prevents the situation in which the area of the substrate 10 shouldbe increased by the area occupied by the protrusion 11 a of the firstadhesion layer 11, which is observed in the conventional embodiments, sothat a smaller-size multilayer-chip-type semiconductor device isimplemented. Since the peripheral edge portion of the first adhesionlayer 11 is not protruding from the peripheral edge portion of thesecond semiconductor chip 14, the situation in which the lengths ofwires 15 should be increased, which is also observed in the conventionalembodiment, is prevented. As a result, the influence of wire sweepoccurring in the step of injecting a mold resin 16 in a mold, which willbe described later, can be suppressed and a short circuit between thewires can be prevented so that a semiconductor device with higherreliability is increased.

Although the adhesive composing the second adhesion layer 13 between thefirst and second semiconductor chips 12 and 14 is shown in the state inwhich it has been adhered preliminarily to the back surface of thesecond semiconductor chip 14 in FIG. 3C, the type of the adhesive and aformation method using the adhesive may be those used in the firstembodiment.

FIG. 3D is a view showing the fourth step. In the present step termed awire bonding step, the electrode pads of the substrate 10 and theelectrode pads of the second semiconductor chip 14 are bonded to eachother with the wires 15. As also described in the first and secondembodiments, if a structure is designed such that the lengths of thewires 15 are uniform around the entire circumference of the secondsemiconductor chip 14, exactly the same equipment conditions can be usedfor wiring so that a wiring operation is performed stably, the yieldrate is increased, and the time required for the step is reduced.

FIG. 3E is a view showing the fifth final step. In the present steptermed a sealing step, the mold resin 16 sealing therein the first andsecond semiconductor chips 12 and 14 and the wires 15 is formed. Bycompletely setting the mold resin 16, the semiconductor device iscompleted.

The foregoing description has been given to the case where a liquidresin is used as the adhesive composing the first adhesion layer 11.This is because, if a liquid adhesive is used, an increase in the amountof outward protrusion of the adhesive is observed remarkably along aspecified edge side of the first semiconductor chip 12. Even if thefirst adhesion layer 11 is composed of a film-like adhesive, however,there is a case where the amount of outward protrusion is larger alongthe specified edge side, which is mainly the case where the positionsand number of the bumps 12 a of the first semiconductor chip 12 arenon-uniform along the four edge sides of the first semiconductor chip12. In this case also, a smaller-size semiconductor device with higherreliability can be implemented by offsetting, to a proper position, thecenter axis A of the second semiconductor chip 14 mounted on the firstsemiconductor chip 12 from the center axis B of the first semiconductorchip 12.

Although the description has been given to the case where the amount ofoutward protrusion of outward the first adhesion layer 11 is largestalong that one of the edges of the first semiconductor chip 12 whichserves as an injection hole for the adhesive composing the firstadhesion layer 11, the amount of outward protrusion of the firstadhesive layer 11 may also be larger along, e.g., two of the four edgesof the first semiconductor chip 12. This is because a smaller-sizesemiconductor device with higher reliability can be implemented ineither case by mounting the second semiconductor chip 14 on the firstsemiconductor chip 12 such that, if the amounts of protrusion along thetwo edges are the same, the protrusion 11 a of the first adhesion layer11 from either one of the two edges does not protrude outwardly beyondthe peripheral edge portion of the second semiconductor chip 14 and, ifthe amount of outward protrusion is larger along either one of the twoedges, the protrusion 11 a of the first adhesion layer 11 from the edgewith a larger amount of outward protrusion does not protrude outwardlybeyond the peripheral edge portion of the second semiconductor chip 14.

Although the description has been given to the case where the planconfiguration of each of the first and second semiconductor chips 12 and14 is a square with reference to FIGS. 3A to 3E, even if the planconfiguration is a rectangle, a smaller-size semiconductor device withhigher reliability can be implemented by mounting the secondsemiconductor chip 14 on the first semiconductor chip 12 such that theperipheral edge portion of the second semiconductor chip 14 protrudesbeyond the peripheral edge portion of the first semiconductor chip 12.It is not necessary for each of the four edge sides of the secondsemiconductor chip 14 to protrude beyond the peripheral edge portion ofthe first semiconductor chip 12. A smaller-size semiconductor devicewith higher reliability can be implemented by mounting the secondsemiconductor chip 14 on the first semiconductor chip 12 such that theportion of the peripheral edge of the protrusion 11 a of the firstadhesion layer 11, which is most outwardly protruding along one of thefour side edges of the first semiconductor chip 12, does not protrudebeyond the corresponding one of the edge sides of the secondsemiconductor chip 14.

EMBODIMENT 4

A semiconductor device according to a fourth embodiment of the presentinvention will be described with reference to FIG. 4.

FIG. 4 is a view showing a multilayer-chip-type semiconductor deviceaccording to the fourth embodiment.

In the present semiconductor device, a square first semiconductor chip12 having bumps 12 a is mounted with the bumps 12 a facing downward on asquare substrate 10 having electrode pads on the upper surface thereofand lands 10 b on the lower surface thereof with a first adhesion layer11 interposed therebetween. A square second semiconductor chip 14 havingelectrode pads 14 a along the peripheral edge of the upper surfacethereof is mounted on the first semiconductor chip 12 with a secondadhesion layer 13 interposed therebetween. The electrode pads 14 a ofthe second semiconductor chip 14 and the electrode pads of the substrate10 are electrically bonded to each other with wires 15. A square thirdsemiconductor chip 19 having electrode pads along the peripheral edgeportion of the upper surface thereof is mounted on the secondsemiconductor chip 14 with a third adhesion layer 18 interposedtherebetween. The electrode pads of the third semiconductor chip 19 andthe electrode pads of the substrate 10 are electrically bonded to eachother with wires 20. The first, second, and third semiconductor chips12, 14, and 19 and the wires 15 and 20 are sealed with a mold resin 16,whereby the semiconductor device having the semiconductor chips stackedin three layers is formed.

In the semiconductor device having the semiconductor chips stacked inthree layers also, the multilayer-chip-type semiconductor device can bereduced in size and the reliability thereof can be increased bydisposing the second semiconductor chip 14 on the first semiconductorchip 12 in consideration of the protruding length and height of theprotrusion 11 a of the first adhesion layer 11 such that the peripheraledge portion of the second semiconductor chip 14 is protruding outwardlyat least beyond the peripheral edge portion of the first semiconductorchip 12.

Even in the case where the third and second semiconductor chips 19 and14 are bonded to each other by using wires or even in the case where thethird semiconductor chip 19 is mounted with the circuit formationsurface thereof opposing the circuit formation surface of the secondsemiconductor chip 14 and flip chip bonding is provided therebetween byusing the bumps, a smaller-size multilayer-chip-type semiconductordevice with higher reliability can also be implemented.

In the semiconductor device having the three-level multilayer structureshown in FIG. 4 also, the second and third semiconductor chips 14 and 19are disposed preferably on the first and third semiconductor chips 12and 14 such that the respective center axes of the second and thirdsemiconductor chips 14 and 19 are in superimposed relation with thecenter axis of the substrate 10 in the same manner as in the first andsecond embodiments.

1-6. (canceled)
 7. A method for fabricating a semiconductor device, themethod comprising: a first step of disposing a first semiconductor chipon a substrate having an electrode pad; a second step of injecting anadhesive in a space between the substrate and the first semiconductorchip to form a first adhesion layer composed of the adhesive and havinga peripheral edge portion protruding outwardly from the firstsemiconductor chip; a third step of mounting, on the first semiconductorchip, a second semiconductor chip having an electrode pad on aperipheral edge portion of an upper surface thereof with a secondadhesion layer interposed therebetween; a fourth step of bonding theelectrode pad of the substrate and the electrode pad of the secondsemiconductor chip to each other with a wire; and a fifth step ofsealing the first and second semiconductor chips and the wire with amold resin, the third step including the step of protruding a peripheraledge portion of the second semiconductor chip outwardly beyond aperipheral edge portion of the first semiconductor chip.
 8. The methodof claim 7, wherein the third step includes the step of protruding theperipheral edge portion of the second semiconductor chip outwardlybeyond the peripheral edge portion of the first adhesion layer.
 9. Themethod of claim 7, wherein the first step includes the step of disposingthe first semiconductor chip such that a center of the firstsemiconductor chip is offset from a center of the substrate in adirection of an edge of the first semiconductor chip opposite to adirection of an edge thereof from which the adhesive is injected in thesecond step.
 10. The method of claim 7, wherein the third step includesthe step of mounting the second semiconductor chip such that a center ofthe second semiconductor chip is offset from a center of the firstsemiconductor chip.
 11. The method of claim 10, wherein the third stepincludes the step of mounting the second semiconductor chip such thatthe center of the second semiconductor chip is offset from the center ofthe first semiconductor chip in a direction of an edge of the firstsemiconductor chip from which the adhesive is injected in the secondstep.
 12. The method of claim 7, wherein the third step includes thestep of mounting the second semiconductor chip such that a center of thesecond semiconductor chip substantially coincides with a center of thesubstrate.